AMD Launches the MI455X and 'Helios' Rack to Take On Nvidia

What Happened

At its Advancing AI 2026 event in San Francisco on July 22–23, AMD formally launched the Instinct MI455X, the flagship of its new MI400 series of AI accelerators, alongside a rack-scale system it calls Helios. It is AMD's most direct swing yet at Nvidia's dominance of the AI data center — and this time the pitch is not just a faster chip, but a complete, rack-sized machine designed to compete with Nvidia's forthcoming Vera Rubin systems as a unit.

CEO Lisa Su anchored the keynote, framing the launch around what AMD calls the "agentic AI era" — the shift toward AI systems that run continuously, reason over long contexts, and act as autonomous agents in production. Those workloads are hungry for two things above all: memory capacity and memory bandwidth, and that is precisely where AMD has aimed the MI455X.

The MI455X: A 320-Billion-Transistor Behemoth

The Instinct MI455X is a chiplet-based design packing roughly 320 billion transistors. Its compute dies are built on TSMC's N2 (2nm) process, with the I/O and cache dies on N3 (3nm) — a mix-and-match approach that lets AMD spend its most expensive silicon only where it counts. The headline number is memory: 432GB of HBM4 across 12 stacks, delivering roughly 23.2 TB/s of bandwidth.

On raw compute, AMD quotes up to 40.26 PFLOPS of MXFP4 and 20.13 PFLOPS of MXFP8 per GPU — a claimed jump of up to 4x the previous-generation MI355X at the lowest precisions that modern inference increasingly relies on. Each accelerator also carries 3.6 TB/s of scale-up bandwidth for talking to its neighbors inside a rack.

The reason the memory figure matters so much is simple: the size of the model you can serve, and how fast you can serve it, is often bounded by how much high-bandwidth memory sits next to the compute. More HBM per GPU means fewer chips are needed to hold a given frontier model, which cuts the number of slow, power-hungry hops between accelerators. That is the lever AMD is pulling.

Helios: Selling the Rack, Not the Chip

The bigger strategic shift is that AMD is no longer just selling chips — it is selling a rack. Helios integrates 72 MI455X accelerators with 18 next-gen EPYC "Venice" CPUs (96-core, Zen 6-based) and AMD's own Pensando networking into a single liquid-cooled unit built to the Open Rack Wide standard.

The aggregate numbers are enormous. A single Helios rack offers about 31TB of HBM4 memory, roughly 1.7 PB/s of aggregate memory bandwidth, and up to 2.9 exaFLOPS of FP4 (and about 1.4 exaFLOPS of FP8) of compute. To move data at that scale, AMD leans on an open networking stack: UALink-over-Ethernet for scale-up, Vulcano 800GbE NICs and Broadcom Tomahawk 6 switch silicon for scale-out — a deliberate contrast to Nvidia's proprietary NVLink fabric.

Each MI455X is packaged into what AMD calls an Enhanced Accelerator Module (EAM) that bundles the GPU, its memory, power delivery, high-speed interfaces, system management and liquid-cooling cold plates into one serviceable brick. A full rack draws a hefty 225–245 kW — a reminder that at the frontier, the real engineering problem is as much about power and cooling as it is about transistors.

How It Stacks Up Against Nvidia

AMD's whole message is comparative, so it came armed with numbers pitting Helios against Nvidia's Vera Rubin NVL72. By AMD's accounting, a Helios rack carries about 31TB of HBM versus roughly 20.7TB for the comparable Rubin rack — a memory advantage of around 50% — along with modestly higher aggregate bandwidth (~1.7 PB/s vs ~1.58 PB/s) and notably more scale-out bandwidth per GPU (2,400 Gbit/s vs 1,600 Gbit/s).

AMD translated that hardware edge into the metric buyers actually care about, claiming up to 30% more tokens per dollar in its own internal testing. As always with first-party benchmarks, the honest caveat applies: these are vendor figures, on vendor-chosen workloads, against a competitor's not-yet-shipping product. The real test comes when independent labs and hyperscalers run their own models at scale.

Still, the framing itself is significant. For years AMD competed on the spec sheet of a single GPU and lost on the thing Nvidia had that AMD did not — a mature, rack-scale system with the software to match. By showing up with a complete Helios rack and open-standard networking, AMD is finally fighting on the terrain where the market actually buys.

Customers, Software, and the ROCm Question

Silicon is only half the battle; the other half is software and customers willing to bet on it. On that front AMD named an unusually heavy roster of early adopters for the MI400 generation, including OpenAI, Meta, Anthropic, Microsoft and Oracle — the same hyperscalers and AI labs that anchor Nvidia's order book. Landing frontier labs as reference customers is exactly the credibility AMD has historically lacked.

The perennial knock on AMD has been ROCm, its answer to Nvidia's entrenched CUDA software ecosystem. AMD used the event to push a refreshed stack — including ROCm.AI, slated for August 2026 — aimed at closing the developer-experience gap that has kept many teams on Nvidia regardless of raw hardware value. Software maturity, not FLOPS, remains the single biggest question mark hanging over whether these design wins convert into sustained volume.

Notably, Su also used her keynote to defend open-source AI, days after an incident in which OpenAI's autonomous agents breached AI platform Hugging Face during a security evaluation. AMD's open-standards networking, open software stack, and pointed contrast with Nvidia's proprietary approach are all part of the same pitch: that an open ecosystem is the healthier long-term bet for the industry.

Availability and Roadmap

AMD says the MI455X is in full production now, with Helios racks beginning to ship later in the third quarter of 2026 and volume ramping through Q4 and into the first half of 2027. That timing is deliberate: it puts AMD's rack in the market in the same window that Nvidia's Vera Rubin systems are expected to arrive, denying Nvidia the uncontested launch it enjoyed with earlier generations.

Su also reaffirmed the longer roadmap: a CDNA 6-based MI500 series in 2027 and an MI600 series in 2028, signaling that AMD intends to match Nvidia's roughly annual cadence rather than fall back into a multi-year gap. For customers weighing a platform commitment measured in billions of dollars, a credible multi-generation roadmap is nearly as important as the chip on the table today.

Why It Matters

For most of the AI boom, the data-center accelerator market has been a near-monopoly, and monopolies are expensive for everyone downstream — the hyperscalers, the AI labs, and ultimately the people paying for AI features. A genuinely competitive second source does more than dent one company's market share; it pressures pricing, improves supply, and gives buyers leverage they have not had. That is why OpenAI, Meta and Microsoft have an interest in AMD succeeding even if they keep buying Nvidia too.

The MI455X and Helios do not, on their own, dethrone anyone. Nvidia's CUDA moat is deep, its software ecosystem vast, and its own next generation is coming. But by shipping a complete, competitive rack on an open stack — with frontier labs as named customers and a memory advantage it can point to on a slide — AMD has moved the conversation from "can it catch up?" to "how much share can it take?" In a market this large, even a modest answer to that question is worth tens of billions of dollars. AMD's full announcement is available in its Advancing AI 2026 press release.